Corner sequence - a P-admissible floorplan representation...

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2003 / 08 Vol. 11; Iss. 4

Corner sequence - a P-admissible floorplan representation with a worst case linear-time packing scheme

Jai-Ming Lin,, Yao-Wen Chang,, Shih-Ping Lin,
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Volume:
11
Language:
english
Journal:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
DOI:
10.1109/tvlsi.2003.816137
Date:
August, 2003
File:
PDF, 752 KB
english, 2003
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