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[IEEE 2008 IEEE International High Level Design Validation and Test Workshop (HLDVT) - Incline Village, NV, USA (2008.11.19-2008.11.21)] 2008 IEEE International High Level Design Validation and Test Workshop - Temporal parallel gate-level timing simulation
Kim, Dusung, Ciesielski, Maciej, Kyuho Shim,, Seiyang Yang,Year:
2008
Language:
english
DOI:
10.1109/hldvt.2008.4695886
File:
PDF, 393 KB
english, 2008