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[IEEE 2005 Symposium on VLSI Technology - Kyoto, Japan (2005.06.14-2005.06.16)] Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005. - Layout impact on the performance of a locally strained PMOSFET
Eneman, S., Verheyen, P., Rooyackers, R., Nouri, F., Washington, L., Degraeve, R., Kaczer, B., Moroz, V., De Keersgieter, A., Schreutelkamp, R., Kawaguchi, M., Kim, Y., Samoilov, A., Smith, L., Absil,Year:
2005
Language:
english
DOI:
10.1109/.2005.1469196
File:
PDF, 404 KB
english, 2005