[IEEE 2008 International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA) - Hilo, HI, USA (2008.01.21-2008.01.23)] 2008 International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems - Design and Power Performance Evaluation of On-Chip Memory Processor with Arithmetic Accelerators
Takahashi, Chikafumi, Sato, Mitsuhisa, Takahashi, Daisuke, Boku, Taisuke, Ukawa, Akira, Nakamura, Hiroshi, Aoki, Hidetaka, Sawamoto, Hideo, Sukegawa, NaonobuYear:
2008
Language:
english
DOI:
10.1109/iwia.2008.9
File:
PDF, 283 KB
english, 2008