[IEEE 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07) - Bangalore, India (2007.01.6-2007.01.10)] 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07) - Fault Coverage and Fault Efficiency of Transistor Shorts using Gate-Level Simulation and Test Generation
Higami, Yoshinobu, Saluja, Kewal, Takahashi, Hiroshi, Takamatsu, YuzoYear:
2007
Language:
english
DOI:
10.1109/vlsid.2007.83
File:
PDF, 252 KB
english, 2007