An automatic test pattern generator for minimizing...

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 2002 / 08 Vol. 21; Iss. 8

An automatic test pattern generator for minimizing switching activity during scan testing activity

Seongmoon Wang,, Gupta, S.K.
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Volume:
21
Language:
english
Journal:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
DOI:
10.1109/tcad.2002.800460
Date:
August, 2002
File:
PDF, 429 KB
english, 2002
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