[Japan Soc. Appl. Phys 2001 Symposium on VLSI Technology. Digest of Technical Papers - Kyoto, Japan (12-14 June 2001)] 2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184) - DRAM scaling-down to 0.1 μm generation using bitline spacerless storage node SAC and RIR capacitor with TiN contact plug
Beom-Jun Jin,, Young-Pil Kim,, Byeong-Yun Nam,, Hyoung-Joon Kim,, Young-Wook Park,, Joo-Tae Moon,Year:
2001
Language:
english
DOI:
10.1109/vlsit.2001.934982
File:
PDF, 359 KB
english, 2001