[IEEE 2010 International Symposium on Electronic System Design (ISED 2010) - Bhubaneswar (2010.12.20-2010.12.22)] 2010 International Symposium on Electronic System Design - Low-Cost Design of Serial-Parallel Multipliers Over GF(2^m) Using Hybrid Pass-Transistor Logic (PTL) and CMOS Logic
Meher, P K, Shen-Fu Hsiao,, Chia-Sheng Wen,, Ming-Yu Tsai,Year:
2010
Language:
english
DOI:
10.1109/ised.2010.33
File:
PDF, 374 KB
english, 2010