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[IEEE 2014 IEEE Symposium on VLSI Circuits - Honolulu, HI, USA (2014.6.10-2014.6.13)] 2014 Symposium on VLSI Circuits Digest of Technical Papers - A 512-kb 1-GHz 28-nm partially write-assisted dual-port SRAM with self-adjustable negative bias bitline
Tanaka, Shinji, Ishii, Yuichiro, Yabuuchi, Makoto, Sano, Toshiaki, Tanaka, Koji, Tsukamoto, Yasumasa, Nii, Koji, Sato, HirotoshiYear:
2014
Language:
english
DOI:
10.1109/vlsic.2014.6858411
File:
PDF, 641 KB
english, 2014