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[IEEE 2010 IEEE Symposium on VLSI Circuits - Honolulu, HI, USA (2010.06.16-2010.06.18)] 2010 Symposium on VLSI Circuits - A DPLL-based per core variable frequency clock generator for an eight-core POWER7™ microprocessor
Tierno, Jose, Rylyakov, Alexander, Friedman, Daniel, Chen, Ann, Ciesla, Anthony, Diemoz, Timothy, English, George, Hui, David, Jenkins, Keith, Muench, Paul, Rao, Gaurav, Smith, George, Sperling, MichaYear:
2010
Language:
english
DOI:
10.1109/vlsic.2010.5560342
File:
PDF, 283 KB
english, 2010