[IEEE 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems - Vienna, Austria (2010.04.14-2010.04.16)] 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems - Memory optimizations for packet classification algorithms in FPGA
Pus, Viktor, Blaho, Juraj, Korenek, JanYear:
2010
Language:
english
DOI:
10.1109/ddecs.2010.5491765
File:
PDF, 304 KB
english, 2010