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[IEEE ESSCIRC 2007 - 33rd European Solid-State Circuits Conference - Muenchen, Germany (2007.09.11-2007.09.13)] ESSCIRC 2007 - 33rd European Solid-State Circuits Conference - Half VDD Clock-Swing Flip-Flop with Reduced Contention for up to 60% Power Saving in Clock Distribution
Levacq, David, Muhammad Yazid,, Hiroshi Kawaguchi,, Makoto Takamiya,, Takayasu Sakurai,Year:
2007
Language:
english
DOI:
10.1109/esscirc.2007.4430277
File:
PDF, 532 KB
english, 2007