A Low Power Logic-Compatible Multi-Bit Memory Bit Cell...

IEEE Transactions on Circuits and Systems I: Regular Papers 2014 / 12 Vol. 61; Iss. 12

A Low Power Logic-Compatible Multi-Bit Memory Bit Cell Architecture With Differential Pair and Current Stop Constructs

Lynch, John, Irazoqui, Pedro P.
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Volume:
61
Language:
english
Journal:
IEEE Transactions on Circuits and Systems I: Regular Papers
DOI:
10.1109/tcsi.2014.2334791
Date:
December, 2014
File:
PDF, 2.23 MB
english, 2014
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