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[IEEE Comput. Soc 7th Asia and South Pacific Design Automation Conference. 15h International Conference on VLSI Design - Bangalore, India (7-11 Jan. 2002)] Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design - Identifying redundant wire replacements for synthesis and verification
Radecka, K., Zilic, Z.Year:
2002
Language:
english
DOI:
10.1109/aspdac.2002.994972
File:
PDF, 349 KB
english, 2002