![](/img/cover-not-exists.png)
[IEEE Symposium on VLSI Technology - Kyoto, Japan (1997.06.12-1997.06.12)] Symposium on VLSI Technology - A Robust 0.15/spl mu/m CMOS Technology With CoSi/sub 2/ Salicide And Shallow Trench Isolation
Kawaguchi,, Abiko,, Inoue,, Saito,, Yamamoto,, Hayashi,, Masuoka,, One,, Tamura,, Tokunaga,, Yamada,, Yoshida,, Sakai,Year:
1997
Language:
english
DOI:
10.1109/vlsit.1997.623730
File:
PDF, 343 KB
english, 1997