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[IEEE 2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation & Test (VLSI-TSA-DAT) - Hsinchu, Taiwan (27-29 April 2005)] 2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test, 2005. (VLSI-TSA-DAT). - Test pattern generation and clock disabling for test time and power reduction
Ji-Jan Chen,, Kun-Lun Luo,, Yeong-Jar Chang,, Wen-Ching Wu,Year:
2005
Language:
english
DOI:
10.1109/vdat.2005.1500057
File:
PDF, 890 KB
english, 2005