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[IEEE 2010 International Symposium on System-on-Chip - SOC - Tampere, Finland (2010.09.29-2010.09.30)] 2010 International Symposium on System on Chip - State chart refinement validation from approximately timed to cycle callable models
Findenig, Rainer, Ecker, WolfgangYear:
2010
Language:
english
DOI:
10.1109/issoc.2010.5625551
File:
PDF, 431 KB
english, 2010