[IEEE 2006 IEEE International Symposium on Circuits and Systems - Island of Kos, Greece (21-24 May 2006)] 2006 IEEE International Symposium on Circuits and Systems - Multilevel timing-constrained full-chip routing in hierarchical quad-grid model
Jin-Tai Yan,, Yen-Hsiang Chen,, Chia-Fang Lee,, Ming-Ching Huang,Year:
2006
Language:
english
DOI:
10.1109/iscas.2006.1693864
File:
PDF, 5.40 MB
english, 2006