[IEEE 2007 IEEE Symposium on VLSI Circuits - Kyoto, Japan (2007.06.14-2007.06.16)] 2007 IEEE Symposium on VLSI Circuits - A Sub-600mV, Fluctuation tolerant 65nm CMOS SRAM Array with Dynamic Cell Biasing
Bhavnagarwala, Azeez, Kosonocky, Stephen, Chan, Yuen, Stawiasz, Kevin, Srinivasan, Uma, Kowalczyk, Steve, Ziegler, MattYear:
2007
Language:
english
DOI:
10.1109/vlsic.2007.4342773
File:
PDF, 2.42 MB
english, 2007