A theoretical yield model for assembly process of area...

IEEE Transactions on Electronics Packaging Manufacturing 2005 / 10 Vol. 28; Iss. 4

A theoretical yield model for assembly process of area array solder interconnect packages with experimental verification

Chunho Kim,, Baldwin, D.F.
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Volume:
28
Language:
english
Journal:
IEEE Transactions on Electronics Packaging Manufacturing
DOI:
10.1109/tepm.2005.856659
Date:
October, 2005
File:
PDF, 1.73 MB
english, 2005
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