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[IEEE EM) - Macao, China (2010.12.7-2010.12.10)] 2010 IEEE International Conference on Industrial Engineering and Engineering Management - Order-lot pegging heuristics for minimizing total tardiness in a semiconductor wafer fabrication facility
Kim, J-G., Lim, S-K., Shim, S-O., Choi, S-W.Year:
2010
Language:
english
DOI:
10.1109/ieem.2010.5674360
File:
PDF, 673 KB
english, 2010