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[Japan Soc. Appl. Phys 2001 Symposium on VLSI Technology. Digest of Technical Papers - Kyoto, Japan (12-14 June 2001)] 2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184) - Scalability and biasing strategy for CMOS with active well bias
Shih-Fen Huang,, Wann, C., Yu-Shyang Huang,, Chih-Yung Lin,, Schafbauer, T., Shui-Ming Cheng,, Yao-Ching Cheng,, Vietzke, D., Eller, M., Chuan Lin,, Quiyi Ye,, Rovedo, N., Biesemans, S., NguyenYear:
2001
Language:
english
DOI:
10.1109/vlsit.2001.934972
File:
PDF, 267 KB
english, 2001