A 10-Gb/s CML I/O Circuit for Backplane Interconnection in...

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2009 / 05 Vol. 17; Iss. 5

A 10-Gb/s CML I/O Circuit for Backplane Interconnection in 0.18-$\mu$m CMOS Technology

Min-Sheng Kao,, Jen-Ming Wu,, Chih-Hsing Lin,, Fan-Ta Chen,, Ching-Te Chiu,, Hsu, S.S.H.
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Volume:
17
Language:
english
Journal:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
DOI:
10.1109/tvlsi.2009.2016726
Date:
May, 2009
File:
PDF, 2.06 MB
english, 2009
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