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Fault simulation and test generation in combinational...

Fault simulation and test generation in combinational circuits using atomic digraphs

VILLAR, E., BRACHO, S.
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Volume:
59
Language:
english
Journal:
International Journal of Electronics
DOI:
10.1080/00207218508920717
Date:
October, 1985
File:
PDF, 186 KB
english, 1985
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