[IEEE 2011 IEEE 9th International Conference on ASIC (ASICON 2011) - Xiamen, China (2011.10.25-2011.10.28)] 2011 9th IEEE International Conference on ASIC - ADDLL/VDD-biasing co-design for process characterization, performance calibration, and clock synchronization in variation-tolerant designs
Wang, Jinn-Shyan, Yung-Chen Chien,, Jia-Hong Lin,, Cheng, Chun-Yuan, Ying-Ting Ma,, Chung-Hsun Huang,Year:
2011
Language:
english
DOI:
10.1109/asicon.2011.6157119
File:
PDF, 1.17 MB
english, 2011