[IEEE 2006 IEEE International Symposium on Circuits and...

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[IEEE 2006 IEEE International Symposium on Circuits and Systems - Island of Kos, Greece (21-24 May 2006)] 2006 IEEE International Symposium on Circuits and Systems - Self-sampled vernier delay line for built-in clock jitter measurement

Kuo-Hsing Cheng,, Chan-Wei Huang,, Shu-Yu Jiang,
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Year:
2006
Language:
english
DOI:
10.1109/iscas.2006.1692904
File:
PDF, 4.33 MB
english, 2006
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