[IEEE 2011 Design, Automation & Test in Europe - Grenoble (2011.03.14-2011.03.18)] 2011 Design, Automation & Test in Europe - Temporal parallel simulation: A fast gate-level HDL simulation using higher level models
Dusung Kim,, Ciesielski, M, Kyuho Shim,, Seiyang Yang,Year:
2011
Language:
english
DOI:
10.1109/date.2011.5763251
File:
PDF, 506 KB
english, 2011