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[IEEE 2008 3rd International Design and Test Workshop (IDT) - Monastir, Tunisia (2008.12.20-2008.12.22)] 2008 3rd International Design and Test Workshop - Power-delay efficient technology mapping of BDD-based circuits using DCVSPG cells
Reddy, Gopal Paul Rohit, Ghosh, Jyotirmoy, Mandal, Ajit Pal C. R., Bhattacharya, Bhargab B.Year:
2008
Language:
english
DOI:
10.1109/idt.2008.4802481
File:
PDF, 736 KB
english, 2008