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[IEEE 2014 IEEE Symposium on VLSI Technology - Honolulu, HI, USA (2014.6.9-2014.6.12)] 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers - Study of the impact of charge-neutrality level (CNL) of grain boundary interface trap on device variability and P/E cycling endurance of 3D NAND flash memory
Chen, Wei-Chen, Lue, Hang-Ting, Hsiao, Yi-Hsuan, Lin, Xi-Wei, Huang, Jacky, Shih, Yen-Hao, Lu, Chih-YuanYear:
2014
Language:
english
DOI:
10.1109/vlsit.2014.6894345
File:
PDF, 6.02 MB
english, 2014