[IEEE 2007 International Symposium on VLSI Design, Automation and Test - Hsinchu, Taiwan (2007.04.25-2007.04.27)] 2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) - Interleaving of Gate Sizing and Constructive Placement for Predictable Performance
Kim, Sungjae, Shragowitz, Eugene, Karypis, George, Lin, Rung-BinYear:
2007
Language:
english
DOI:
10.1109/vdat.2007.373225
File:
PDF, 3.37 MB
english, 2007