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[IEEE 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005. - Grenoble, France (Sept. 12-16, 2005)] Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005. - A 10Mbit, 15Gbytes/sec bandwidth 1R DRAM chip with planar MOS storage capacitor in an unmodified 150nm logic process for high-density on-chip memory applications
Somasekhar, D., Shih-Lien Lu,, Bloechel, B., Dermer, G., Lai, K., Borkar, S., Vivek De,Year:
2005
Language:
english
DOI:
10.1109/esscir.2005.1541633
File:
PDF, 323 KB
english, 2005