Design of Efficient Content Addressable Memories in...

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2015 / 5 Vol. 23; Iss. 5

Design of Efficient Content Addressable Memories in High-Performance FinFET Technology

Bhattacharya, Debajit, Bhoj, Ajay N., Jha, Niraj K.
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Volume:
23
Language:
english
Journal:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
DOI:
10.1109/tvlsi.2014.2319192
Date:
May, 2015
File:
PDF, 1.99 MB
english, 2015
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