[IEEE 2014 IEEE Symposium on VLSI Circuits - Honolulu, HI, USA (2014.6.10-2014.6.13)] 2014 Symposium on VLSI Circuits Digest of Technical Papers - A 4.25GHz–4.75GHz calibration-free fractional-N ring PLL using hybrid phase/current-mode phase interpolator with 13.2dB phase noise improvement
Nandwana, Romesh Kumar, Anand, Tejasvi, Saxena, Saurabh, Seong-Joong Kim,, Talegaonkar, Mrunmay, Elkholy, Ahmed, Woo-Seok Choi,, Elshazly, Amr, Hanumolu, Pavan KumarYear:
2014
Language:
english
DOI:
10.1109/vlsic.2014.6858446
File:
PDF, 524 KB
english, 2014