TRANSISTOR LEVEL MODELING FOR ANALOG/RF IC DESIGN || Compact modeling in Verilog-A
GRABINSKI, WLADYSLAW, NAUWELAERS, BART, SCHREURS, DOMINIQUEVolume:
10.1007/1-
Year:
2006
Language:
english
DOI:
10.1007/1-4020-4556-5_10
File:
PDF, 225 KB
english, 2006