[IEEE 2014 NORCHIP - Tampere (2014.10.27-2014.10.28)] 2014 NORCHIP - Synthesis and layout of an asynchronous network-on-chip using Standard EDA tools
Muller, Christoph Thomas, Kasapaki, Evangelia, Sorensen, Rasmus Bo, Sparso, JensYear:
2014
Language:
english
DOI:
10.1109/NORCHIP.2014.7004742
File:
PDF, 643 KB
english, 2014