Layout-versus-schematic verification for superconductive...

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Layout-versus-schematic verification for superconductive integrated circuits

Roberts, Rebecca, Fourie, Coenrad
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Year:
2014
Language:
english
Journal:
IEEE Transactions on Applied Superconductivity
DOI:
10.1109/tasc.2014.2373035
File:
PDF, 652 KB
english, 2014
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