Modeling and Separate Extraction Technique for Gate...

IEEE Transactions on Electron Devices 2015 / 3 Vol. 62; Iss. 3

Modeling and Separate Extraction Technique for Gate Bias-Dependent Parasitic Resistances and Overlap Length in MOSFETs

Lee, Jungmin, Bae, Hagyoul, Hwang, Jun Seok, Ahn, Jaeyeop, Jang, Jun Tae, Yoon, Jinsoo, Choi, Sung-Jin, Kim, Dae Hwan, Kim, Dong Myong
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Volume:
62
Language:
english
Journal:
IEEE Transactions on Electron Devices
DOI:
10.1109/TED.2015.2388704
Date:
March, 2015
File:
PDF, 1.62 MB
english, 2015
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