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[IEEE 2014 Conference on Design of Circuits and Integrated Systems (DCIS) - Madrid, Spain (2014.11.26-2014.11.28)] Design of Circuits and Integrated Systems - A high throughput configurable partially-parallel decoder architecture for Quasi-Cyclic Low-Density Parity-Check Codes
Hariri, Alaa Aldin Al, Monteiro, Fabrice, Sieler, Loic, Dandache, AbbasYear:
2014
Language:
english
DOI:
10.1109/DCIS.2014.7035602
File:
PDF, 2.30 MB
english, 2014