Compact modeling of 0.35 μm SOI CMOS technology...

Microelectronic Engineering 2010 Vol. 87; Iss. 12

Compact modeling of 0.35 μm SOI CMOS technology node for 4 K DC operation using Verilog-A

A. Akturk, M. Peckerar, K. Eng, J. Hamlet, S. Potbhare, E. Longoria, R. Young, T. Gurrieri, M.S. Carroll, N. Goldsman
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Volume:
87
Year:
2010
Language:
english
Pages:
7
DOI:
10.1016/j.mee.2010.06.005
File:
PDF, 1.68 MB
english, 2010
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