Circuit level prediction of device performance degradation...

Microelectronics Reliability 2007 Vol. 47; Iss. 6

Circuit level prediction of device performance degradation due to negative bias temperature stress

Rihito Kuroda, Akinobu Teramoto, Kazufumi Watanabe, Michihiko Mifuji, Takahisa Yamaha, Shigetoshi Sugawa, Tadahiro Ohmi
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Volume:
47
Year:
2007
Language:
english
Pages:
7
DOI:
10.1016/j.microrel.2006.06.013
File:
PDF, 382 KB
english, 2007
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