Effects of low gate bias annealing in NBT stressed...

Microelectronics Reliability 2009 Vol. 49; Iss. 9-11

Effects of low gate bias annealing in NBT stressed p-channel power VDMOSFETs

I. Manić, D. Danković, S. Djorić-Veljković, V. Davidović, S. Golubović, N. Stojadinović
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Volume:
49
Year:
2009
Language:
english
Pages:
5
DOI:
10.1016/j.microrel.2009.07.010
File:
PDF, 375 KB
english, 2009
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