A Novel Low-Power Logic Circuit Design Scheme

IEEE Transactions on Circuits and Systems II Analog and Digital Signal Processing 2007 / 02 Vol. 54; Iss. 2

A Novel Low-Power Logic Circuit Design Scheme

Starzyk, Janusz A., He, Haibo
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Volume:
54
Language:
english
Journal:
IEEE Transactions on Circuits and Systems II: Express Briefs
DOI:
10.1109/tcsii.2006.883093
Date:
February, 2007
File:
PDF, 366 KB
english, 2007
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