![](/img/cover-not-exists.png)
Folded fully depleted FET using Silicon-On-Nothing technology as a highly W-scaled planar solution
G. Bidal, N. Loubet, C. Fenouillet-Beranger, S. Denorme, P. Perreau, D. Fleury, L. Clement, C. Laviron, F. Leverd, P. Gouraud, S. Barnola, R. Beneyton, A. Torres, C. Duluard, J.D. Chapon, B. Orlando,Volume:
53
Year:
2009
Language:
english
Pages:
6
DOI:
10.1016/j.sse.2009.02.010
File:
PDF, 897 KB
english, 2009