A design-oriented timing jitter/skew model in...

Analog Integrated Circuits and Signal Processing 2015 / 1 Vol. 82; Iss. 1

A design-oriented timing jitter/skew model in voltage-to-time converter (VTC) circuits

Mostafa, Hassan, Ismail, Yehea I.
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Volume:
82
Language:
english
Journal:
Analog Integrated Circuits and Signal Processing
DOI:
10.1007/s10470-014-0465-z
Date:
January, 2015
File:
PDF, 920 KB
english, 2015
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