Low Power, Low Chip Area, Digital Distance Calculation...

Solid State Phenomena 2013 / 3 Vol. 199

Low Power, Low Chip Area, Digital Distance Calculation Circuit for Self-Organizing Neural Networks Realized in the CMOS Technology

Długosz, Rafał, Kolasa, Marta, Talaśka, Tomasz, Pauk, Jolanta, Wojtyna, Ryszard, Szulc, Michał, Gugała, Karol, Farine, Pierre André
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Volume:
199
Language:
english
Journal:
Solid State Phenomena
DOI:
10.4028/www.scientific.net/ssp.199.247
Date:
March, 2013
File:
PDF, 501 KB
english, 2013
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