An automated high-level topology generation procedure for...

Integration, the VLSI Journal 2010 Vol. 43; Iss. 3

An automated high-level topology generation procedure for continuous-time ΣΔ modulator

Soumya Pandit, Chittaranjan Mandal, Amit Patra
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Volume:
43
Year:
2010
Language:
english
Pages:
16
DOI:
10.1016/j.vlsi.2010.02.001
File:
PDF, 778 KB
english, 2010
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