Development of low-complexity all-digital frequency locked...

IET Circuits Devices & Systems 2014 / 03 Vol. 8; Iss. 2

Development of low-complexity all-digital frequency locked loop as 500 MHz reference clock generator for field-programmable gate array

Han, Seok-Kyun, Lee, Sang-Gug, Cho, Han-Jin, Yoon, Giwan, Yuwono, Sigit
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Volume:
8
Language:
english
Journal:
IET Circuits, Devices & Systems
DOI:
10.1049/iet-cds.2013.0175
Date:
March, 2014
File:
PDF, 1.13 MB
english, 2014
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