[IEEE 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010) - Dresden (2010.03.8-2010.03.12)] 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010) - BCDL: A high speed balanced DPL for FPGA with global precharge and no early evaluation
Nassar, Maxime, Bhasin, Shivam, Danger, Jean-Luc, Duc, Guillaume, Guilley, SylvainYear:
2010
Language:
english
DOI:
10.1109/date.2010.5456932
File:
PDF, 150 KB
english, 2010