![](/img/cover-not-exists.png)
[IEEE 2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA) - Burlingame, CA, USA (2015.2.7-2015.2.11)] 2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA) - Correction prediction: Reducing error correction latency for on-chip memories
Duwe, Henry, Jian, Xun, Kumar, RakeshYear:
2015
Language:
english
DOI:
10.1109/hpca.2015.7056055
File:
PDF, 544 KB
english, 2015