Polysilicon oxide quality optimization at Wafer level of a...

Microelectronics Reliability 2001 Vol. 41; Iss. 9-10

Polysilicon oxide quality optimization at Wafer level of a Bipolar/CMOS/DMOS technology

X. Gagnard, Y. Rey-Tauriac, O. Bonnaud
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Volume:
41
Year:
2001
Pages:
6
DOI:
10.1016/s0026-2714(01)00213-x
File:
PDF, 417 KB
2001
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